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    Wafer pruning set to improve chip manufacturing yields

    The method – called wafer pruning – performs wafer tests earlier in the manufacturing process, rather than after chip packaging. By using process monitors on wafer lines tested after the initial manufacturing steps, manufacturers can evaluate die performance earlier and estimate wafer yield.

    "The notion of design assisted manufacturing is a big change from the way things are done currently," said Puneet Gupta, pictured, professor of electrical engineering at UCLA. "Our research provides a way to not waste resources in producing silicon wafers that will eventually lose money because chips on them are not good enough for production. We believe that the cost reductions from this and other design-assisted manufacturing methods that we are investigating could easily be as much as one full technology node